Vertically interconnected parallel distributed processor

ABSTRACT

A parallel distributed processor comprises matrices of unit cells arranged in a stacked configuration. Each unit cell includes a chalcogenide body which may be set and reset to a plurality of values of a given physical property. Interconnections between the unit cells are established via the chalcogenide materials and the pattern and strength of the interconnections is determined by the set values of the chalcogenide. The processor is readily adapted to the construction of neural network computing systems.

FIELD OF THE INVENTION

This invention relates generally to computers and more particularly toparallel distributed processors. More specifically, the inventionrelates to a multi-layered, vertically interconnected, paralleldistributed processor which allows the implementation of neural networkcomputers in which the degree of connectivity between individual neuronsthereof may be set and reset over a large dynamic range resulting in acomputer having the ability to learn from, and adapt to, various datainputs.

BACKGROUND OF THE INVENTION

Digital data processors operate in a serial, algorithmic mode and arecapable of performing complex calculations very accurately and quickly.Such processors are incorporated in serial computers generally referredto as von Neumann type machines and they implement data manipulations ina step-by-step fashion. Many information processing problems can besolved by this approach, particularly those requiring repetitivecalculations; however, von Neumann type computers perform inadequatelywhen doing tasks involving pattern recognition, classification orassociative learning. A further drawback of von Neumann type computersis presented by the fact that before a problem is amenable to solution,it must be fully understood and reduced to a series of algorithms andthe algorithms must be translated into an appropriate language forprocessing by a particular computer. Construction of an appropriatealgorithm for tasks involving interpretation of patterns, particularlydynamically changing patterns such as those encountered in speechrecognition, high speed character recognition and interpretation ofmoving scenery present extremely difficult, if not impossible, tasks.

The brain of even a relatively simple organism represents a dataprocessor operating in a parallel, distributed mode and it is capable ofquickly and accurately interpreting a large body of dynamically changingdata without the need for input of a complex algorithm. Such operationis even more impressive in view of the fact that signal propagation inthe brain occurs at a speed many orders of magnitude lower than thespeed of propagation of an electrical signal in a silicon chip.Biological neural systems are characterized by a very high degree ofconnectivity and signal processing is effected by both the degree andarchitecture of these connections as well as their ability to be alteredand reconfigured by specific stimuli.

Investigations of biological systems have led to the development ofneural computing networks also termed "parallel, distributed dataprocessors." Such networks are characterized by the presence of a largenumber of individual computing elements typically termed "neurons,""unit cells," or "nodes." These individual cells are each interconnectedto a plurality of other unit cells in a complex network. Connectionsbetween pairs of unit cells may be characterized as weak or strong andalso as excitory or inhibitory. By the addition of the appropriate inputand output circuitry to one or more neural processors, a neural networkcomputer may be constructed. However, efforts made heretofore toconstruct neural network computers have led to complex software and havebeen hampered by inadequate hardware.

Neural network computing systems are trained to perform a particulartask, rather than being programmed to execute an algorithm. Training isaccomplished by configuring the pattern of connections betweenindividual neurons. Training may be done in a passive mode by simplypresetting the pattern, and in some instances the strength, of theconnections between individual unit cells so as to elicit a desiredresponse to a particular input. A more sophisticated approach involves adynamic method wherein the actual output response of the network to agiven input signal is correlated with a desired output response togenerate a training signal which is then applied to the network toreconfigure the connections. A network of this type is able to "learn"an appropriate response to a given input stimulation. A dynamicallytrainable system can learn from its mistakes and is capable of a largedegree of self-teaching.

While it is generally agreed that the massively parallel non-linearlogic of neural network computers will readily adapt them to a widevariety of practical applications involving pattern recognition, speechsynthesis and the solving of multi-parameter problems, the actualimplementation of neural network information processing systems has beenhampered by a lack of appropriate computing hardware. Presently, mostinvestigations into neural network computing systems are carried out byemulating neural network systems on conventional von Neumann typecomputers. While such simulation allows for testing of particular neuralnetwork architectures, the conventional digital computer, operating in aserial manner, inherently presents a bottleneck to the paralleldistributed processing approach of neural network systems. In someinstances, dedicated computing systems comprised of a plurality ofprocessors arranged in a parallel relationship have been utilized forneural network simulations. While these types of machines do confer someadvantages in terms of speed, they do not provide true distributedprocessing and they still cannot simulate fully a large scale, highlyinterconnected, reconfigurable array of neurons. Furthermore, they arelimited by the interconnect problem associated with increasing numbersof nodes, as will be explained more fully hereinbelow.

It is desirable to fabricate large scale, parallel, distributed dataprocessors which comprise integrated arrays of interconnectable unitcells. The unit cells themselves are generally very simple devices fortransferring data from one conductor to another, but the processor mustbe capable of establishing a complex pattern of interconnectionstherebetween. Two dimensional structures are not capable of providing asufficiently large number of nodes to permit massively parallel, highlyinterconnected networks to be prepared; therefore three-dimensionalstructures are desired. Furthermore, computing power of the processor isgreatly enhanced if the degree of connectivity between individualneurons may be controlled over a large dynamic range.

Heretofore, the art has not been adequate to enable the construction oflarge three-dimensional processing arrays of this type. If the switchingof connections and the control of the degree of connectivity of aparallel distributed processor is implemented through the use ofconventional semiconductor circuitry, the complexity of each unit cellincreases significantly, thereby limiting the size and number of unitcells in a network. It would clearly be desirable to control theconnection between individual unit cells through a simple, reliablecircuit element which may be set to a range of values corresponding todifferent connectivities.

One attempt to provide a configurable neural network is disclosed byThakoor et al in a Jet Propulsion Laboratory report numbered "JPLD-4166(1987)" entitled "Content-Addressable High Density Memories Based onNeural Network Models." This approach relies upon an amorphous tocrystalline transition first recognized by S. R. Ovshinsky, (see forexample, "Reversible Electrical Switching Phenomena in DisorderedStructures" Physical Review Letters V.21, N20, November 1968). Thedevice of Thakoor et al. comprises a two-dimensional matrix ofprogrammable amorphous silicon resistors interconnecting a series ofsimple unit cells. Each resistor is initially in a high resistivitystate and may be set to a lower resistivity state by an appropriatepulse of current. By appropriately setting the resistors, the network isprogrammed; however, the resistors are not resettable hence, the systemis not capable of being reconfigured or otherwise operating in a dynamiclearning mode. Also, the resistors are not settable across a dynamicrange of resistances and fine control of the degree of connectivitybetween interconnected cells is not possible.

Accordingly, it will be appreciated that there is a need for a simpleneural network processor wherein the degree of connectivity between theunit cells may be simply and reliably set and reset in a cyclic, i.e.repeatable, mode. A system of this type is capable of a high degree ofdynamic learning. It is further desirable that any such processor beadaptable to manufacture by standard device fabrication techniques. Itis highly desirable that this network be structured as a large area,vertically interconnected three-dimensional device so as to increaseprocessing density and decrease operational time.

While researchers have looked to the brain for initial inspiration inthe development of neural network computing systems, they have continuedto blindly rely upon conventional semiconductor structures and materialsto implement these systems. Conventional semiconductor devices andmaterials operate in a volatile mode and are not well suited for neuralcircuitry. S. R. Ovshinsky has long recognized the fact that particularclasses of materials can exhibit a range of physical properties whichare analogous to those of biological neural systems. See, for example,"Analog Models for Information Storage and Transmission in PhysiologicalSystems" by Stanford R. and Iris M. Ovshinsky in Mat. Res. Bull. Vol. 5,pp 681-690 (1970).

It has been found that certain materials, particularlychalcogenide,-based or containing, materials may be selectably,reversibly and cyclically set to a number of different values of avariety of physical properties such as electrical, optical, chemical,acoustic, pressure response and magnetic. In accord with the principlesof the present invention these materials may be used as the basis forthe interconnection of a number of unit cells into a three-dimensionalneural network system. Materials of this type confer heretoforeunattainable advantages in a neural network system insofar as they allowfor ready programming and retraining of systems. Furthermore, thesematerials may be deposited in thin films over relatively large areaswith high degrees of reliability and hence make possible the fabricationof large area, monolithic arrays of stacked unit cells and therebyprovide a high density, massively parallel, distributed processingnetwork.

The history of computing can be divided into phases based upon theproblems presented by the interconnections of computing systems. Theearliest electronic computers employed vacuum tubes and relays and thehigh failure rate, large power dissipation and bulk of these devicesgreatly restricted the number of nodes or connection points in theseprimitive systems. The development of the transistor made possiblesmaller, more reliable computing system thereby increasing the number ofnodes and signal processing capabilities of such later computers.Integrated circuit technology made possible the inclusion of a verylarge number of transistors on a single chip and this greatly increasedboth the number of nodes and their degree of connectedness therebymaking parallel processing systems possible.

The advent of parallel processing has raised the art to a point where anew barrier of connectivity has arisen which limits further developmentof such systems. Like the brain, realistic neuronal models should havenodes with unit dimensions on the order of square microns and shouldhave a high degree of complex and reconfigurable interconnectivity.(See: S. R. Ovshinsky and I. M. Ovshinsky), "Analog Models forInformation Storage and Transmission in Physiological Systems" Mat. Res.Bull. Vol. 5, pp 681-690 (1970, Pergamon Press)). Intelligence ofneuronal systems is proportional to the number of nodes or neurons inthe system as well as to the number of interconnections to which eachnode is a party. Furthermore, the information processing ability of thenetwork is greatly increased if the nodes are interconnected in ananalog manner whereby the strength of the interconnections may be variedover a range of values.

Through the present invention, previous problems of interconnectivityare overcome and it is now possible to provide a compact, highlyinterconnected neural network in which the connectivity between thevarious nodes may be adjusted and readjusted over a large dynamic range.

The computing systems provided by the present invention are truelearning machines, unlike other parallel processors, insofar as they canadapt their connectivity to changing inputs in order to learn and cansynthesize a creative output in response to novel stimuli. The systemsof the present invention have utility in pattern recognition, adaptivecontrol systems and in a wide variety of problem solving tasks.

These and other advantages of the present invention will be readilyapparent from the drawings, discussion and description which follow.

BRIEF DESCRIPTION OF THE INVENTION

There is disclosed herein a parallel processing network comprisingparallel distributed processing means in communication with data inputmeans and operative to receive and process a parallel input of data. Theprocessing means includes a three-dimensional array of stacked planes ofunit cells aligned in a repetitive, electrically interconnected pattern.Each unit cell includes data input means, data output means and a bodyof chalcogenide based material selectively and reversibly settable overa range of distinguishable values of a given physical property. The bodyof chalcogenide material is disposed so as to establish communicationbetween the data input means and the data output means. The paralleldistributed processing means further includes means for establishingcommunication between the data output means of a first one of the unitcells in a first one of the stacked planes and the data input means of asecond one of the unit cells in a second one of the stacked planes.Communication between the unit cells is established through thechalcogenide based material of at least one of the unit cells. In aprocessor of this type, the strength of the connection between the firstand second unit cells is determined by the particular value of thephysical property to which the chalcogenide based material is set. Inparticular embodiments, the network further includes means for settingand resetting the body of chalcogenide based material to one of therange of distinguishable values. The chalcogenide based material may beset to distinguishable values of electrical, optical or magneticproperties. The means for setting the chalcogenide may be in electricalcommunication with the data input means of the unit cell and/or with thedata output means of at least one other unit cell. The unit cells mayalso include an isolation device such as a diode or transistor disposedin an electrical series relationship with the body of chalcogenide basedmaterial.

In particular embodiments, the chalcogenide based material may furtherinclude carbon, silicon, germanium, tin, lead, phosphorous, arsenic,antimony, oxygen or fluorine.

In yet another embodiment of the present invention, each unit cellincludes means for setting and resetting the body of chalcogenide basedmaterial and the setting and resetting means of a first unit cell in afirst one of the stacked planes is in electrical communication with asecond unit cell in a second one of the stacked planes whereby theoutput signal of each unit cell is determined by data communicated fromthe data input mean of that cell and by data communicated from the dataoutput means of at least other unit cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic depiction of a unit cell structured in accordwith the principals of the present invention;

FIG. 1B is a schematic depiction of a portion of two stacked planes ofunit cells;

FIG. 2 is a schematic depiction of another embodiment of unit cellstructured in accord with the principals of the present invention andincluding inhibitory and excitory lines;

FIG. 3 is a schematic depiction of yet another unit cell structured inaccord with the principals of the present invention and including aseparate control line;

FIG. 4 is a schematic depiction of yet another unit cell of the presentinvention including excitory and inhibitory lines controlled by a commoninput line:

FIG. 5 is a schematic, exploded depiction of a neural network computingdevice structured in accord with the principals of the present inventionand including a vertically interconnected parallel distributed processortherein; and

FIG. 6 is a graph depicting the electrical characteristics of a typicaladaptive memory material which may be employed in the practice of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention comprises a vertically interconnected paralleldistributed processing array which includes a plurality of stackedmatrices of unit cells. Each unit cell is in data transmissivecommunication with at least one other unit cell in an adjoining plane.Preferably, the unit cells in a given plane are also interconnected tosome degree. In this manner, a high degree of connectedness betweenindividual unit cells of the array may be established.

Each of the unit cells includes a body of chalcogenide based materialwhich is reversibly settable and resettable over a range ofdistinguishable values of a given physical property such as electricalresistance, capacitance, optical transmission, reflectivity and thelike. The use of a settable and resettable material permits theestablishment of various degrees of connection between individual unitcells.

Referring now to FIG. 1A, there is shown a typical unit cell which maybe employed in the present invention. The unit cell includes a datainput line 10 and a data output line 12. Communication between the twolines 10,12 is established via a body of chalcogenide based material 14.The unit cell further includes an isolation device, such as a diode 16.Typically, the unit cells are arranged in an array wherein the datainput 10 and data output lines 12 comprise a series of rows and columnsand in this embodiment an isolation device 16 functions to prevent crosstalk between adjacent unit cells. The isolation device is depicted asbeing a diode 16, and as such may comprise a thin film diode such as apolycrystalline silicon diode although amorphous, polycrystalline orcrystalline diodes of various other materials may be similarly employedas may be other devices such as transistors. When structures comprisingchalchogenides and polycrystalline diodes are to be fabricated, thediodes are generally deposited as amorphous devices, utilizing thin filmtechnology and they are subsequently crystallized. In accord with thepresent invention, it has been found advantageous to crystallize thediode material through the use of a short pulse of light from a laser orsimilar source so as to rapidly crystallize the material withoutdamaging the chalcogenide material.

The cell of FIG. 1A is part of a matrix of generally identical cellsarranged in rows and columns. The processor of the present inventionincludes a stacked array of such matrices and at least some of the cellsin a first matrix are interconnected with cells in a second matrix sothat the data output of the cell in the first plane 40 communicates withthe input of the cell in a second plane 42. FIG. 1B depicts, inschematic form, a portion of a stacked array of two matrices 40,42, eachincluding unit cells interconnected by a vertical via 44. Similarstacked matrices are contemplated within the scope of the presentinvention for the other unit cells shown herein.

FIG. 2 depicts a unit cell including an excitory 18 input and inhibitory20 input and a data output line 12. This embodiment further includes abody of chalcogenide material 14 and an isolation device 16 associatedwith each of the input lines 18, 20. A unit cell of this type canreceive bipolar data which either stimulates or inhibits an outputresponse. In the foregoing unit cells, the body of chalcogenide basedmaterial is set and reset by signals applied to the data input lines 10,18, 20 and the data output lines 12.

FIG. 3 depicts yet another embodiment of the present invention whichfurther includes a field effect transistor 22 having the source anddrain in series with a data input line 10 and body of chalcogenidematerial 14. The gate 24 of the transistor is energized by a separatecontrol line 26. In a unit cell of this type, data impressed on thecontrol line 26 can further modify or supplement data on the input line10 so as to further influence the setting and resetting of thechalcogenide material 14.

Referring now to FIG. 4 there is shown still another embodiment of unitcell. This cell includes excitory 18 and inhibitory lines 20, eachhaving a field effect transistor 22 having the source and drain thereofin series with a body of chalcogenide material 14 and an isolation diode16. The gates 24 of each of the transistors 22 are controlled by acommon control line 28. In the operation of a unit cell of this type,the common control line 28 receives input data, such as data from apixel of an image sensor and communicates this data to the unit cell.Excitory and inhibitory data on the respective lines 18, 20 modifies thecell's response to this data so as to generate an output which iscommunicated to other cells in the processing net.

It is to be understood that the foregoing is illustrative of particularunit cell configurations which may be employed in the present invention.Other variations of unit cell may be similarly employed. The presentinvention encompasses all parallel distributing processing arrays havinginterconnected unit cells which include a body of settable andresettable chalcogenide based material. The present invention readilylends itself to the fabrication of neural network computing systems aswell as various other parallel processing devices.

Referring now to FIG. 5, there is shown an exploded view schematicallydepicting on particular configuration of neural network computerstructured in accord with the principals of the present invention. Thecomputing device of FIG. 5 is an integrated computing structureparticularly adapted for image sensing and processing. The computingdevice of FIG. 5 includes a sensor array layer 30 which comprises amatrix of photosensitive elements arrayed in a pixel format. The matrixmay be a two-dimensional array, i.e., an n×m array; or, it may be aone-dimensional array, i.e., a 1×n array. The sensor elements maycomprise photoresponsive devices such as an amorphous silicon devices orother thin film devices such as cadmium sulfide, cadmium telluride orcopper indium diselenide photoresponsive devices. The sensor array 30 isdisposed to receive an image thereupon and to generate parallel streamsof data corresponding to the various pixels of the image.

In most instances, the computer includes a second layer 32 ofamplification circuitry comprised of a matrix of amplifier devicescorresponding in number to the photoresponsive elements of the sensorarray 30. The amplification layer 32 is operative to amplify theparallel data streams generated by the sensor layer 30. Disposed inelectrical communication with the amplifier layer 32 is the verticallyinterconnected parallel processing network 34 described hereinabove. Theprocessing network 34 is comprised of a number of stacked planes, eachplane comprising a matrix of unit cells corresponding generally to theelements of the sensor array. The parallel data streams from the sensorarray are amplified and pass to the topmost portion of the parallelprocessing network 34 and proceed from the individual unit cells in thefirst plane to one or more unit cells in the second plane and thenceonto further planes in the processing network 34. As was describedhereinabove, the strength of interconnections between cells insuperposed planes are controlled via chalcogenide based elements. Theparallel distributing processing network 34 includes a number of stackedplanes, each plane comprising a matrix of unit cells. It is to beunderstood that the number of unit cells in the various planes may beidentical or may vary. In some instances, it is desirable to have a unitplane in a stacked relationship with a greater or lesser number of unitcells in an adjoining plane and such variations are contemplated withinthe scope of the present invention.

The parallel processing network 34 is disposed upon a silicon substrate36, shown schematically herein as a silicon wafer. The silicon substrateincludes the drive circuitry, multiplexing circuitry and interconnectcircuitry for establishing communication with the processing network 34.The substrate 36 can further include output contacts or leads, not shownin this illustration. Silicon is a preferred material for the substratelayer since the high speed of crystalline silicon circuitry confersadvantages in the operation of the computing device; although it is tobe understood that other substrate layers, including layers ofsemiconductor material having degrees of order ranging from purelyamorphous to polycrystalline may be similarly employed.

While the FIG. 5 embodiment depicts the sensor array and amplificationlayers as being relatively thin planes, it is to be understood that arepresentation herein is schematic and the sensor array andamplification layer may comprise multiple stacked planes. It is also tobe understood that while sensor array has been described in terms of aphotosensor, other inputs may be similarly provided. For example, thesensor array 30 may be replaced by a matrix of electrical inputs.Alternatively, various other sensing devices may be employed to input asignal corresponding to acoustic, magnetic, thermal, pressure orchemical inputs. For example, the sensor array 30 may be an array ofchemfets. These devices are field effect transistors which respond toparticular chemical species. An array thus configured would be welladapted for sensing chemical species and would have great utility in thecharacterization and classification of odors, detection of bombs, gasesor other noxious species as well as the quantification of aromas such asperfumes, wines and foodstuffs.

The chalcogenide based material is employed to establish communicationbetween the input and output mean of each unit cell and hence becomes acritical link in establishing intracellular communication. Thechalcogenide material may be set over a range of physical properties bethey optical, magnetic or electrical. For example, by an appropriateinput of energy the transparency and/or reflectivity of the material maybe reversibly set to a plurality of values. Similarly, input of anappropriate signal can change the capacitance, resistivity, or magneticpermeability of these materials to different stable values. In the mostpreferred embodiment of the present invention, the computing systemoperates on electrical impulses and the chalcogenide material is set andreset to a plurality of values of electrical resistivity although it isto be understood that in optical computing systems, reflectivity and/oroptical transmission may be similarly employed.

Within the context of the present invention, chalcogenide basedmaterials are defined as being any materials which include one or morechalcogenide elements therein and it is generally understood that thechalcogenide elements include the group VIa elements of the periodictable. The chalcogenide based materials of the present invention canalso include elements such as carbon, silicon, germanium, tin, lead,phosphorous, arsenic, antimony, fluorine, oxygen or bismuth. Oneparticularly preferred group of chalcogenide materials are thosereferred to as adaptive memory materials. These materials are reversiblyswitchable from a highly disordered state to a more ordered state andvarious degrees of local order or disorder correspond to differentvalues of resistivity or other physical properties.

In a typical adaptive semi-conductor material, the resistance may bealtered from a value of about 10⁶ ohms to about 10² ohms by a currentpulse of about 1 millisecond duration having an amplitude of 5 milliampsor by an equivalent pulse of light energy or the like. To obtain anintermediate resistance value, intermediate values of current areapplied.

Referring now to FIG. 6 there is shown a schematic depiction ofelectrical properties of a typical adaptive memory material. The Figuredepicts a plot of the log of the set energy applied to the materialversus the log of the electrical resistivity of the material. It will beseen from the curve that the resistance decreases with increasing setenergy. It will also be seen that the magnitude of the current fluxapplied to the material, even under equal energy conditions, determinesthe final resistance of the material. It will thus be appreciated thatthis material effectively provides a solid state equivalent of arheostat. By using an appropriate current pulse, the resistance value ofthe material may be set to a stable value. By utilizing a material ofthis type in the processor of the present invention, the degree ofconnectivity between individual unit cells may be readily set.

There are a number of compositions of chalcogenide based adaptive memorymaterial which may be employed in the practice of the invention. Theadaptive memory materials generally contain Group IV and/or VIsemi-conductor materials and they further include Group V materials suchas phosphorous. When phosphorous is replaced by a high molecular weightGroup V elements such as arsenic, antimony, etc. the resistance versusenergy curve becomes steeper. Adaptive memory materials are detailed inU.S. Pat. No. 3,530,441 of Ovshinsky, the disclosure of which isincorporated herein by reference. In view of the foregoing it is to beunderstood that large area parallel distributed processing arrays may beadvantageously constructed utilizing adaptive, settable and resettablechalcogenide materials. These arrays have significant utility in theconstruction of neural network computing systems as well as other dataprocessing applications. The foregoing drawings, discussion, descriptionand examples are merely illustrative of particular embodiments of thepresent invention. It is to be understood that numerous modificationsand variations thereof may be practiced in accord with the principals ofthe present invention. It is the following claims, including allequivalents, which define the scope of the invention.

We claim:
 1. A parallel processing network comprising:(A) means for aparallel input of a plurality of data; and (B) parallel distributedprocessing means operative to receive and process said parallel input ofsaid plurality of data, said processing means including:(1) athree-dimensional array of stacked planes of a plurality of unit cells;each of said unit cells is a single repetition of a repetitive,three-dimensional electrically interconnected pattern; each unit cellincluding:(a) data input means; (b) data output means; and (c) a body ofchalcogenide based material which is characterized by the capability ofbeing selectively and reversibly set to any particular distinguishablevalue within a range of distinguishable values of a given physicalproperty, said body of chalcogenide material disposed so as to establishcommunication between said data input means and said data output means;and (2) means for establishing communication between the data outputmeans of a first one of said unit cells in a first one of said stackedplanes and the data input means of a second one of said unit cells in asecond one of said stacked planes, said communication occurring throughthe body of chalcogenide based material of at least one of said unitcells, whereby the strength of the connection between said first andsecond unit cells is determined by the particular distinguishable value,within said range of distinguishable values of said physical property,to which the body of chalcogenide material, through which saidcommunication occurs, is set.
 2. A network as in claim 1, furthercomprising means for setting and resetting said body of chalcogenidebased material to one of said range of distinguishable values.
 3. Anetwork as in claim 2, wherein said means for setting and resettingcomprises means for applying an electrical signal to said body ofchalcogenide based material.
 4. A network as in claim 3, wherein saidmeans for applying an electrical signal to said body of chalcogenidebased material is in electrical communication with the data input meansof the unit cell.
 5. A network as in claim 3, wherein said means forapplying an electrical signal to said body of chalcogenide basedmaterial is in electrical communication with the data output means of atleast one other unit cell.
 6. A network as in claim 2, wherein saidmeans for setting and resetting said body of chalcogenide based materialincludes a field effect transistor.
 7. A network as in claim 6, whereinthe gate of said field effect transistor is in electrical communicationwith the data output means of at least one other unit cell.
 8. A networkas in claim 1, wherein each unit cell further includes isolation meansdisposed in series with said body of chalcogenide based material.
 9. Anetwork as in claim 8, wherein said isolation means comprises atransistor.
 10. A network as in claim 9, wherein said transistor is afield effect transistor.
 11. A network as in claim 8, wherein saidisolation device is a diode.
 12. A network as in claim 11, wherein saiddiode is a polycrystalline silicon diode.
 13. A network as in claim 11,wherein said diode is a microcrystalline diode.
 14. A network as inclaim 1, wherein said means for the parallel input of a plurality ofdata comprises means for the parallel input of electrical data.
 15. Anetwork as in claim 1, wherein the means for the parallel input of aplurality of data comprises means for the parallel input of opticaldata.
 16. A network as in claim 15, wherein the means for the parallelinput of optical data further includes means for converting optical datato electrical data.
 17. A network as in claim 16, wherein said means forconverting optical data to electrical data includes a photoresponsivebody of silicon alloy material.
 18. A network as in claim 1, whereinsaid means for the parallel input of data further includes means forsensing a preselected chemical species and generating an electricalsignal in response thereto.
 19. A network as in claim 1, wherein saidbody of chalcogenide based material is selectively and reversiblysettable over a range of values of electrical resistivity.
 20. A networkas in claim 1, wherein the body of chalcogenide based material isselectively and reversibly settable over a range of values of an opticalproperty.
 21. A network as in claim 1, wherein said body of chalcogenidebased material is selectively and reversibly settable over a range ofvalues of electrical capacitance.
 22. A network as in claim 1, whereinsaid body of chalcogenide based material is selectively and reversiblysettable over a range of values of a magnetic property.
 23. A network asin claim 1, wherein said chalcogenide based body further includescarbon.
 24. A network as in claim 1, wherein said chalcogenide basedbody further includes silicon.
 25. A network as in claim 1, wherein saidchalcogenide based body further includes germanium.
 26. A network as inclaim 1, wherein said chalcogenide based body further includes tin. 27.A network as in claim 1, wherein said chalcogenide based body furtherincludes lead.
 28. A network as in claim 1, wherein said chalcogenidebased body further includes phosphorus.
 29. A network as in claim 1,wherein said chalcogenide based body further includes arsenic.
 30. Anetwork as in claim 1, wherein said chalcogenide based body furtherincludes antimony.
 31. A network as in claim 1, wherein saidchalcogenide based body further includes fluorine.
 32. A network as inclaim 1, wherein said chalcogenide based body further includes bismuth.33. A network as in claim 1, wherein said data input means is anexcitory data input means and wherein said each unit cell furtherincludes second data input means for the input of inhibitory data and asecond body of chalcogenide based material selectively and reversiblysettable over a range of distinguishable valves of a given physicalproperty, disposed so as to establish communication between said seconddata input means and said data output means.